Quad flat no lead (QFN) grid array package, method of making and memory module and computer system including same

ABSTRACT

A quad flat no-lead (QFN) grid array semiconductor package and method for making the same. The package includes a semiconductor die and a lead frame having conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die are coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and a portion of at least a portion of the lead frame are encapsulated in an insulative material leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to semiconductorpackaging. More specifically, the present invention relates tosemiconductor packaging using a quad-flat package design incorporating alead frame and providing an increased number of input/output contactsarranged in a grid array.

[0003] 2. State of the Art

[0004] Conventional quad flat packages (QFP) are formed with asemiconductor die connected to a lead frame and being encapsulated toform a package such that a plurality of leads extends laterallyoutwardly from each side of the periphery of the encapsulatingstructure. Such a configuration is relatively simple in design and maybe efficiently produced. However, the QFP-type semiconductor has shownvarious design and production limitations. For example, reducing theoverall package size of a QFP becomes difficult because of thearrangement of leads about the lateral periphery of the package. This isparticularly evident when reduced package size is attempted to becombined with increasing the number of input/output (I/O) connectionsrequired for the smaller yet ever more complex dice representing thestate of the art.

[0005] In order to either reduce the size of a conventional QFP while atleast maintaining, if not increasing, the number of connections or toincrease the number of I/O connections while at least maintaining, ifnot decreasing, the package size, a higher density of connections wouldbe required along the package perimeter. However, such an increaseddensity of leads about the package perimeter inherently requires areduced pitch or spacing between adjacent leads and promotes anincreased likelihood of cross-talk and signal interference as well asmaking such packages more difficult to fabricate.

[0006] In an effort the increase the number of connections in anintegrated circuit (IC) package while maintaining or decreasing theoverall size, alternative packaging arrangements have been implemented.For example, grid array devices such as pin grid arrays (PGA's), ballgrid arrays (BGA's), land grid arrays (LGA's) and their associatedvariants have been used to reduce package size while and increaseinput/output connections. As an example of a grid array type device, aBGA device employs a number of input/output connections in the form ofconductive bumps, such as solder balls, extending transversely from amajor surface of the package in a pattern, or “array,” of columns androws. The conductive bumps may be formed on one surface of a circuitboard or other interposer substrate and are in electrical connectionwith bonding pads on the opposing surface of the circuit board. Asemiconductor die is coupled to the bonding pads, such as by wirebonding, to establish electrical connections from the bond pads of thesemiconductor die to the conductive bumps. The resulting assembly isthen typically encapsulated such as by transfer molding with a filledpolymer with the array of conductive bumps being left exposed forsubsequent electrical connection to higher level packaging such as acarrier substrate. The conductive bumps are configured to be coupled toa mirror image pattern of terminal pads on the carrier substrate whichmay comprise a printed circuit board (PCB) or another structure byreflowing the solder. In essence, a BGA device increases the number ofinput/output connections by allowing the connections to be positionedover substantially the entirety of a major surface of the package ratherthan extending laterally outwardly from the periphery of the packagesuch as in a QFP.

[0007] While BGA and other grid array devices provide an increasednumber of input/output connections and may allow a simultaneousreduction in size for a given package, such devices are not withouttheir own limitations and drawbacks. For example, the use of circuitboard interposers, upon which the array of conductive elements isformed, imposes limitations on the size of the package since the circuitboard is typically larger than the semiconductor die. Additionally, thecircuit boards used in making BGA packages have been known to take onmoisture during the fabrication process leading to subsequent crackingand warpage which ultimately renders the device unusable. Furthermore,the cost of circuit boards used in the fabrication of grid array typedevices may also may also be viewed as a drawback.

[0008] In view of the shortcomings in the art, it would be advantageousto provide a semiconductor die package which allowed for a higherdensity of input/output connections without increasing package size. Itwould further be advantageous to provide such a package having apatterned array of input/output connections formed from a lead frame.

[0009] Additionally, it would be advantageous to provide a method ofproducing such a package, and the lead frame utilized such a package,which does not require significant changes in tooling or fabricationprocesses such that the method is easily and efficiently implementedwithout incurring significant capital costs for new equipment or anincrease in process steps.

BRIEF SUMMARY OF THE INVENTION

[0010] One aspect of the invention includes a method of forming asemiconductor die or integrated circuit package. The method includesproviding a semiconductor die having a plurality of bond pads located onan active surface thereof. A lead frame having a plurality of conductiveleads is provided adjacent the semiconductor die. A first bond bad onthe semiconductor die is electrically coupled to a first portion of atleast one conductive lead and a second bond pad is coupled to a secondportion of the same lead. The first portion and second portion of thelead are then electrically isolated from one another to form twoindividual conductive elements from the original conductive lead.Additionally, an insulative encapsulant may be formed about thesemiconductor die and at least partially about the lead frame whileallowing a portion of each individual conductive element to remainexposed for subsequent electrical coupling with an external electricalcircuit such as a carrier substrate.

[0011] The individual conductive elements may, for example, beelectrically isolated from one another by saw cutting the conductivelead subsequent to the first and second portion being coupled to thebond pads of the semiconductor die. Also, a severance region may bepredefined in the lead between the first portion and second portion soas to help facilitate the electrical isolation of the two portions. Theseverance region may include a notch or recess formed by scoring,cutting or etching partially through the material of the lead.Encapsulant covering the semiconductor die may be extended into thenotch or recess of the severance region prior to isolating the firstportion and second portion to help retain the first portion and secondportion in their respective positions once they have been separated fromone another by complete removal of any intervening lead material.

[0012] Another aspect of the present invention includes a method offorming an array of electrically conductive elements for an integratedcircuit package. The method includes disposing a semiconductor diehaving a plurality of bond pads on an active surface thereof on a leadframe including a plurality of leads. At least two bond pads of thesemiconductor die are electrically coupled with each lead of the leadframe. The leads are then severed between the locations of coupling toform at least two electrically isolated conductive elements, each suchelectrically isolated conductive element being coupled to an individualbond pad on the semiconductor die.

[0013] The present invention also includes a lead frame of a firstdesign. The lead frame includes a plurality of individual leads. Atleast one of the plurality of leads includes a first bonding region, asecond bonding region and a severance region located between the firstand second bonding regions. The severance region is configured tofacilitate separation of the first bonding region from the secondbonding region subsequent to connection of bond pads of a semiconductordie to the respective first and second bonding regions and encapsulationof the lead frame and semiconductor die to form an integrated circuitpackage.

[0014] The present invention further includes a lead frame of a seconddesign. This lead frame includes a die paddle configured for attachmentof a semiconductor die thereto. The lead frame also includes a pluralityof conductive elements each having at least two bonding regions. Thebonding regions are arranged in a grid array pattern which includes afirst peripheral row of bonding regions spaced about a periphery of thedie paddle and at least one other peripheral row of bonding regionsspaced laterally outwardly from the first peripheral row.

[0015] Yet another aspect of the invention includes a semiconductor dieor integrated circuit package. The integrated circuit package includes asemiconductor die, a lead frame and an electrically insulativeencapsulant. The lead frame includes a plurality of spaced conductiveelements arranged in an array including a first set of conductiveelements on a major surface of the package and adjacent a lateralperiphery thereof and at least one other set of conductive elementsinwardly adjacent the first set. The insulative encapsulant extends overthe semiconductor die and at least partially over the lead frame whileallowing a portion of each of the conductive elements to be exposed onthe major surface for connection with an external electrical circuit. Atleast one concavity or other recess is defined between and electricallyisolates at least one conductive element of the first set and anadjacent conductive element of the at least one other set.

[0016] In accordance with another aspect of the invention anotherintegrated circuit package is provided. The integrated circuit packageincludes a semiconductor die having a plurality of bond pads and a leadframe having a plurality of conductive leads. Each of the plurality ofleads is electrically coupled to at least two bond pads of the pluralityof bond pads.

[0017] In accordance with another aspect of the present invention amemory module is provided. The memory module includes a carriersubstrate in the form of a module board configured to be electricallycoupled to another, higher level packaging structure such as amotherboard, enabling the memory module to communicate with a processor.At least one integrated circuit package having features such as thosedescribed above is electrically coupled to the module board.

[0018] In accordance with another aspect of the invention, a computersystem is provided. The computer system comprises an input device, anoutput device, a processor coupled to the input and output devices, anda memory module, such as described above, coupled with the processor.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0019] The foregoing and other advantages of the invention will becomeapparent upon reading the following detailed description and uponreference to the drawings in which:

[0020]FIG. 1 is a plan view of the bottom of an IC package according toone embodiment of the present invention;

[0021]FIG. 2 is a cross-sectional view of the IC package of FIG. 1;

[0022]FIGS. 3A and 3B are enlarged views of the section specified inFIG. 2 at various stages of manufacturing;

[0023]FIGS. 4A and 4B are plan views of an IC package according toalternative embodiments;

[0024]FIG. 5 is a plan view of a lead frame strip according to oneembodiment of the present invention; and

[0025]FIG. 6 is schematic of a computer system incorporating the ICpackage of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0026]FIGS. 1 and 2 depict one embodiment of an integrated circuitpackage of the present invention in the form of a quad flat no-lead(QFN) grid array package 10. FIG. 1 presents a view of a major surfacecomprising the underside of the QFN package 10, while FIG. 2 shows across section of the QFN package 10 taken along section line 2-2 asshown in FIG. 1. The QFN package 10 includes a semiconductor die 12positioned on and secured by its back side to a die paddle 14, diepaddle 14 originally comprising a portion of a lead frame as will behereinafter described. Conductive elements 16 are positioned about thedie paddle 14 in a grid array pattern, outwardly of semiconductor die 12and adjacent the lateral periphery of QFN package 10. The die paddle 14and conductive elements 16 may be formed of any suitable material suchas copper, aluminum, alloy 42 or any other suitable conductive materialfor lead frames as understood by those of ordinary skill in the art.

[0027] The grid array pattern of the conductive elements 16 may bedescribed in various geometrical terms such as a grid having a specifiednumber columns and rows. However, due to the general placement of theconductive elements 16 outwardly of the semiconductor die 12 andgenerally adjacent the periphery of the QFN package 10, the grid arraystructure will be discussed in terms of peripheral rows. Thus, the QFNpackage 10 shown in FIGS. 1 and 2 includes a first inner peripheral row18A and a second outer peripheral row 18B of conductive elements 16.

[0028] The language “peripheral row” is used herein for convenience indescribing the configuration of the QFN package 10 and should not beunderstood as requiring all of the conductive elements 16 to be locatedat or on the peripheral edge of the QFN package 10, nor should suchphraseology be taken to mean the that a given peripheral row ofconductive elements 16 must circumscribe the entire die paddle 14 andsemiconductor die. While it is desirable to have the conductive elements16 positioned about each side of the QFN package 10 so as to maximizethe number of conductive elements 16 in the package, some designs maynot require such an arrangement. Alternatively, some configurations mayinclude peripheral rows that only partially circumscribe the die paddle14 and semiconductor die 12, such as arrangements where peripheral rowslie on opposing sides of the QFN package 10.

[0029] The conductive elements 16 are each conductively coupled to abond pad 22 on the active surface of semiconductor die 12 such as bywire bonds 24. The semiconductor die 12 and wire bonds 24 areencapsulated with an electrically insulative (dielectric) material 26which also partially encapsulates the conductive elements 16, extendingbetween die paddle 14 and the inner peripheral row 18A of conductiveelements 16, between the inner peripheral row 18A of conductive elements16 and the outer peripheral row 18B of conductive elements 16 andbetween laterally adjacent conductive elements 16 of each of theperipheral rows 18A and 18B. The encapsulant material 26 may comprise asilicon particle-filled polymer encapsulant applied under heat andpressure by transfer molding, as well known in the art.

[0030] The conductive elements 16 each have an exposed surface 28 on thebottom major surface of the QFN package 10 for subsequent electricalcoupling with another electrical component such as a carrier substrate(not shown). Such connection may be made, for example, through the useof conductive bumps 28 b, shown in broken lines for clarity. Such bumpsmay include, for example, solder bumps which are stenciled ontoconductive elements 16 and then reflowed to form balls, conductive orconductor-filled epoxy columns or pillars, or self-supporting spheres(either conductive or insulative) covered with a conductive material. Itis further contemplated that an anisotropic, so-called “Z-axis”conductive material comprising laterally-spaced conductive elements in adielectric film and oriented transversely to the plane thereof may alsobe employed to connect conductive elements 16 to a carrier substrate.All of the foregoing approaches, and others, are known to those ofordinary skill in the art and are not to be taken as limiting of thepresent invention.

[0031] The inner peripheral rows 18A and outer peripheral rows 18B ofconductive elements 16 adjacent each edge of QFN package 10 are shown tobe separated from one another by an elongated, trough-like concavity orrecess 30. As shown in FIG. 2, the concavity or recess 30 is formed asan elongated saw cut or scribe line extending from a first lateral edgeof the QFN package 10 to an opposing lateral edge. However, theconcavity may be formed according to other techniques known in the artsuch as, for example, a masking and etching process. In the embodimentshown in FIGS. 1 and 2, the concavity or recess 30 serves to create theindividual conductive elements 16 of the two peripheral rows 18A and 18Bfrom a single row of individual, laterally extending leads of a leadframe. The fabrication process can be seen more clearly with referenceto FIGS. 3A and 3B. FIG. 3A depicts a partial section of the QFN package10 showing the QFN package 10 at a stage in fabrication prior toformation of the individual conductive elements 16. The QFN packageshown in FIG. 3A includes a single lead 16′ rather than individualconductive elements 16. It is further noted that there are multiple wirebonds 24 connected to different bonding regions 32, 34 of the lead 16′.A severance region 36, shown as an upward-facing notch, is preformed inthe lead 16′ and subsequently filled with encapsulant 26 subsequent toattachment of semiconductor die 12 to die paddle 14 and wire bonding ofa bond pad 22 (not shown in FIG. 3A) to bonding regions 32, 34. Thenotch of severance region 36 may be formed by various processes such assaw cutting, scribing, scoring or etching of the lead 16′ prior toencapsulation of the lead 16′ and wire bond 24 and preferably prior toattachment of semiconductor die 12 to die paddle 14.

[0032] Subsequent to the application of encapsulant 26 the lead 16′ maybe severed, such as through the aforementioned saw cutting or etching,to form individual, electrically isolated conductive elements 16 asshown in FIG. 3B. Each conductive element 16 is connected to a wire bond24 and thus to a bonding pad 22 of the semiconductor die 12. It is notedthat the severance region 36 serves various purposes. First, theseverance region 36 identifies an area of separation on the lead 16′.This helps to identify the individual bonding regions 32, 34 during wirebonding of the lead 16′ to the bond pads 22 of the semiconductor die 12.Additionally, the severance region 36 allows for the formation of a moreshallow concavity or recess 30 during the separation of the lead 16′into individual conductive elements 16, such as to minimize thepotential for damage to QFN package 10. Also, by forming theupward-facing notch in the severance region 36 prior to encapsulation,the transfer-molded encapsulant 26 flows under pressure into the notchand substantially laterally about at least three sides of the ultimatelocation of each conductive element 16 to form a structural member 38between and about the locations of individual conductive elements 16 tomore effectively tie the conductive elements 16 to encapsulant 26,precisely fixing their locations and enabling the package to withstandthe stresses placed on leads 16′ without damage thereto or movementthereof.

[0033] While the severance region 36 is desirably in the form of a notchor recess as shown, it is contemplated that the severance region 36 ofthe lead 16′ may simply be a designated area of separation without anotch or other physical feature. It is noted that in such a case, theconcavity or recess 30 extending upwardly from the bottom major surfaceof QFN package 10 would penetrate through the entire thickness of thelead 16′ and there would be no encapsulant 26 formed between theadjacent inner and outer individual conductive elements 16 to serve as astructural member 38. If desired, a structural member 38 could be formedafter the formation of the concavity 30 by filling same with dielectricmaterial regardless of whether or not an upwardly-facing, preformednotch or recess in each lead 16′ is used to facilitate the formation ofindividual conductive elements 16.

[0034] Referring to FIGS. 4A and 4B alternative embodiments are shownwith regard to the grid array pattern. FIG. 4A shows the bottom surfaceof a QFN package 10′ having three different peripheral rows 18A, 18B and18C of conductive elements 16. The conductive elements 16 are formed ina similar manner as described above except that additional severanceregions 36 (or notches) would be located in each lead 16′ and that thereare additional concavities 30 to assist in forming the third peripheralrows 18C.

[0035]FIG. 4B shows the bottom surface of a QFN package 10″ also havingthree peripheral rows 18A′,18B′ and 18C′. However, in the embodiment ofFIG. 4B the conductive elements 16″ of the peripheral rows 18A′, 18B′and 18C′ are staggered such that a conductive element 16″ in peripheralrow 18B′ is shifted slightly to one side as compared to an adjacentconductive element 16″ in peripheral row 18A′. Similarly, a conductiveelement 16″ in peripheral row 18C′ is shifted slightly to one side ascompared to an adjacent conductive element 16″ in peripheral row 18B′.Such an arrangement is possible by forming a lead frame having leads 16′positioned at an angle other than perpendicular with respect to anadjacent edge of the die paddle 14. The individual peripheral rows 18A′,18B′ and 18C′ are formed in a manner similar to that described above,with elongated, trough-like concavities 30 being formed to ultimatelycreate the individual conductive elements 16″. The staggeredconfiguration serves to allow more flexibility in wire bondingconfigurations and potentially lower bond loop heights due to thelateral staggering of the conductive elements 16. Thus, depending on theangle at which a lead 16′ is formed on a lead frame, the offset of oneperipheral row relative to another may be controlled and wire bondingconfigurations may be flexibly designed.

[0036] Referring now to FIG. 5, an exemplary lead frame strip 50including a plurality of individual lead frames 52 for use in formingQFN packages 10 is shown. The multiple lead frames 52 are formed in asingle, longitudinally extending strip 50 as is known by those ofordinary skill in the art. Each lead frame 52 includes an outer frameportion 52 o bearing a die paddle 14 supported substantially in thecenter thereof by tie bars and multiple inwardly extending, cantileveredleads 16′. A reduced number of leads 16′ is shown for clarity, but isnot intended to be limiting of the invention. The leads 16′ are eachformed with a severance region 36, such as a notch or similar recess,for subsequent formation of individual conductive elements 16 from theleads 16′. As discussed above, the severance regions 36 may be formed byvarious techniques such as scoring, saw cutting, or etching. Theseverance regions 36 define the locations of the peripheral rows 18A and18B which will be subsequently formed in the QFN package 10. The leadframes 52 depicted in FIG. 5 are representative of a lead frame 52 whichmight be used in the formation of a QFN package 10 described inconjunction with FIGS. 1 and 2. Other lead frames of suitableconfiguration and with similar features would be utilized in forming theQFN packages 10′, 10″ discussed in conjunction with FIG. 4A or 4Brespectively as is understood by those of ordinary skill in the art. Infabricating QFN packages of the present invention, the outer frameportions 52 o are severed from the packages to effect electricalisolation of die paddle 14 as well as each set of conductive elements 16from the outer frame portions 52 o, while mutual electrical isolationbetween the conductive elements 16 formed from each lead 16′ is effectedby cutting through the leads 16′ from the lead surfaces opposite thenotches of severance regions 36. To facilitate alignment of the packagesfor creating the concavities or recesses 30, it is preferred currentlythat QFN packages 10 be severed from outer frame portions 52 o aftersuch concavities or recesses are cut or otherwise formed. If conductivebumps 28 b are to be formed or placed on conductive elements 28, it mayalso be desirable to form or place conductive bumps 28 b while QFNpackages 10 are still unsevered from lead frame strip 50 to facilitatealignment and handling.

[0037] Referring now to drawing FIG. 6, a schematic of an electronicsystem 60, such as a personal computer, including an input device 62(such as a keyboard and mouse) and an output device 64 (such as adisplay or printer interface) coupled or otherwise in electricalcommunication with a processor device 66, is illustrated. Processordevice 66 is also coupled or otherwise in operable electricalcommunication such as through traces of a motherboard with one or morememory modules 68 incorporating a plurality of QFN packages according tothe present invention such as 10, 10′, 10″ or variations thereof. Thememory module 68 may include a memory board 70 having an electricalcircuit formed therein, such as a PCB. Furthermore, processor device 66may be directly embodied in a module with a QFN package whichincorporates the teachings hereof and further include, withoutlimitation, a microprocessor, a first level cache memory, and additionalintegrated circuits, such as logic circuits, a video processor, an audioprocessor, or a memory management processor.

[0038] While the invention may be susceptible to various modificationsand alternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

What is claimed is:
 1. A method of fabricating an integrated circuitpackage comprising: providing a semiconductor die having a plurality ofbond pads on an active surface thereof, providing a lead frame includinga plurality of conductive leads; electrically coupling a first bond padof the plurality of bond pads to a first portion of at least oneconductive lead; electrically coupling a second bond pad of theplurality of bond pads to a second portion of the at least oneconductive lead; and electrically isolating the first portion of the atleast one conductive lead from the second portion of the at least oneconductive lead.
 2. The method of claim 1, further comprisingencapsulating the semiconductor die and at least a portion of the leadframe in a dielectric material.
 3. The method of claim 2, wherein theelectrically isolating the first portion from the second portion iseffected subsequent to the encapsulating.
 4. The method of claim 1,wherein the electrically isolating the first portion from the secondportion of the at least one conductive lead includes mechanicallysevering the at least one conductive lead between the first portion andthe second portion.
 5. The method of claim 1, wherein the electricallyisolating the first portion from the second portion of the at least oneconductive lead includes etching to sever the at least one conductivelead between the first portion and the second portion.
 6. The method ofclaim 1, wherein the electrically coupling the first bond pad to a firstportion of the at least one conductive lead includes wire bonding. 7.The method of claim 6, wherein electrically coupling the second bond padto a second portion of the at least one conductive lead includes wirebonding.
 8. The method of claim 1, further comprising forming a notchedregion in a surface of the at least one conductive lead between thefirst portion and the second portion.
 9. The method of claim 8, furthercomprising encapsulating the semiconductor die and at least a portion ofthe lead frame including the notched region of the at least oneconductive lead in a dielectric material.
 10. The method of claim 9,wherein the electrically isolating the first portion from the secondportion includes separating the first portion from the second portionwhile leaving at least some dielectric material in the notched region.11. The method of claim 10, wherein the separating the first portionfrom the second portion includes cutting the at least one conductivelead into the notched region from an opposing surface of the at leastone conductive lead.
 12. A method of forming an array of electricallyconductive elements on an integrated circuit package, the methodcomprising: securing a semiconductor die having a plurality of bond padson an active surface thereof to a lead frame having a plurality ofleads; electrically coupling each lead of the plurality of leads atspaced locations with one of at least two different bond pads of theplurality of bond pads; and severing each lead between the spacedlocations to form at least two electrically isolated conductiveelements.
 13. A lead frame comprising: a plurality of leads, includingat least one lead having: a first bonding region, a second bondingregion, and a severance region located between the first bonding regionand the second bonding region, the severance region being configured tofacilitate separation of the first bonding region from the secondbonding region.
 14. The lead frame of claim 13, wherein the severanceregion includes a notch in the lead.
 15. The lead frame of claim 13,wherein each of the plurality of leads include a first bonding region, asecond bonding region, and a severance region configured to facilitateseparation of the first and second bonding regions.
 16. The lead frameof claim 15, wherein each severance region includes a notch.
 17. A leadframe for an integrated circuit package, the lead frame comprising: adie paddle configured for attachment to a semiconductor die; and aplurality of conductive elements each having at least two bondingregions arranged in a grid array about the die paddle, the grid arrayincluding at a first peripheral row of bonding regions spaced about aperiphery of the die paddle and at least one other peripheral row ofbonding regions spaced outwardly from the first peripheral row ofbonding regions.
 18. An integrated circuit package comprising: asemiconductor die; a plurality of conductive elements arranged in anarray, the array including at least a first set of spaced andelectrically isolated conductive elements adjacent an outer lateralperiphery of the integrated circuit package and at least one other setof spaced and electrically isolated conductive elements inwardlyadjacent the first set, the at least two sets of conductive elementsbeing located outside a lateral periphery of the semiconductor die; andielectric encapsulant formed over the semiconductor die and definingthe outer lateral periphery of the integrated circuit package, thedielectric encapsulant extending at least partially laterally about theconductive elements and leaving an outer surface of each conductiveelement exposed; and a recess in the encapsulant material between atleast one conductive element of the first set of conductive elements andat least one adjacent conductive element of the at least one other setof conductive elements.
 19. The integrated circuit package of claim 18,wherein the semiconductor die includes a plurality of bond pads andwherein each of the plurality of bond pads are electrically connectedwith a conductive element of the plurality of conductive elements. 20.The integrated circuit package of claim 19, wherein the electricalconnection between each of the plurality of bond pads and eachrespective conductive element of the plurality of conductive elementsincludes a wire bond.
 21. The integrated circuit package of claim 18,wherein the conductive elements of the first set of conductive elementsare substantially aligned with the conductive elements of the at oneother set transverse to an adjacent outer lateral peripheral edge of theintegrated circuit package.
 22. The integrated circuit package of claim21, wherein the conductive elements of the first set of conductiveelements are offset relative to the conductive elements of the at oneother set.
 23. The integrated circuit package of claim 18, wherein therecess comprises an elongated, trough-like recess extendingsubstantially between conductive elements of the first set andconductive elements of the second set disposed along a common laterallyouter peripheral edge of the integrated circuit package.
 24. Asemiconductor die assembly, comprising: a semiconductor die having aplurality of bond pads; a lead frame having a plurality of conductiveleads, each lead being electrically coupled at spaced locations on thelead to at least two bond pads of the plurality of bond pads.
 25. Theintegrated circuit package of claim 24, further comprising a dielectricencapsulant formed about the semiconductor die and partially about thelead frame.
 26. The integrated circuit package of claim 24, furthercomprising a wire bond coupling each lead at the spaced locationsthereon to one of the at least two bond pads of the plurality of bondpads.
 27. The integrated circuit package of claim 26, wherein each leadincludes a severance region configured to facilitate separation into atleast two mutually electrically isolated conductive elements.
 28. Amemory module comprising: a module board configured to be electricallycoupled with a higher level of packaging; and at least one integratedcircuit package electrically coupled with the module board, theintegrated circuit package comprising: a semiconductor die; a pluralityof conductive elements arranged in an array, the array including atleast a first set of spaced and electrically isolated conductiveelements adjacent an outer lateral periphery of the integrated circuitpackage and at least one other set of spaced and electrically isolatedconductive elements inwardly adjacent the first set, the at least twosets of conductive elements being located outside a lateral periphery ofthe semiconductor die; an dielectric encapsulant formed over thesemiconductor die and defining the outer lateral periphery of theintegrated circuit package, the dielectric encapsulant extending atleast partially laterally about the conductive elements and leaving anouter surface of each conductive element exposed; and a recess in theencapsulant material between at least one conductive element of thefirst set of conductive elements and at least one adjacent conductiveelement of the at least one other set of conductive elements.
 29. Acomputer system comprising: an input device; an output device; aprocessor coupled to the input and output devices; and a memory modulecoupled to the processor, the memory module comprising a module boardcoupled to at least one integrated circuit package comprising: asemiconductor die; a plurality of conductive elements arranged in anarray, the array including at least a first set of spaced andelectrically isolated conductive elements adjacent an outer lateralperiphery of the integrated circuit package and at least one other setof spaced and electrically isolated conductive elements inwardlyadjacent the first set, the at least two sets of conductive elementsbeing located outside a lateral periphery of the semiconductor die; andielectric encapsulant formed over the semiconductor die and definingthe outer lateral periphery of the integrated circuit package, thedielectric encapsulant extending at least partially laterally about theconductive elements and leaving an outer surface of each conductiveelement exposed; and a recess in the encapsulant material between atleast one conductive element of the first set of conductive elements andat least one adjacent conductive element of the at least one other setof conductive elements.
 30. A semiconductor die assembly, comprising: asemiconductor die having a plurality of bond pads on an active surfacethereof; at least one set of mutually spaced conductive elementslaterally outboard of at least one peripheral edge of the semiconductordie, and at least another set of mutually spaced conductive elementsspaced from and laterally outboard of the at least one set of conductiveelements; a plurality of wire bonds extending between bond pads of theplurality and conductive elements of the first and second sets; and apackage comprising dielectric material extending over the semiconductordie and wire bonds and having an outer lateral periphery substantiallycoincident with outer lateral extents of the at least one other set ofconductive elements, dielectric material of the package extending atleast partially about each of the conductive elements and leaving asurface thereof exposed.
 31. The semiconductor die assembly of claim 30,further comprising a die paddle to which the semiconductor die issecured by a back side thereof.
 32. The semiconductor die assembly ofclaim 30, wherein the at least one set of mutually spaced conductiveelements and the at least another set of conductive elements extendaround a plurality of peripheral edges of the semiconductor die.
 33. Thesemiconductor die assembly of claim 30, wherein the at least one set ofmutually spaced conductive elements and the at least another set ofconductive elements extend around four peripheral edges of thesemiconductor die.
 34. The semiconductor die assembly of claim 30,further including an elongated, trough-like recess extending betweenconductive elements of the at least one set and conductive elements ofthe at least another set and substantially parallel to the at least oneperipheral edge of the semiconductor die.
 35. The semiconductor dieassembly of claim 30, wherein the exposed surfaces of the conductiveelements are oriented substantially parallel to the active surface ofthe semiconductor die.
 36. A method of fabricating a semiconductor dieassembly, comprising: placing a semiconductor die within a plurality ofleads extending laterally outwardly from peripheral edges thereof; wirebonding bond pads on the semiconductor die to spaced locations on theleads of the plurality; transfer molding a dielectric encapsulant overthe semiconductor die, wire bonds and leads, leaving undersurfaces ofthe leads exposed; and severing the leads between the spaced locations.37. The method of claim 36, further comprising notching upper surfacesof the leads between the spaced locations before the placing thesemiconductor die within the plurality of leads.
 38. The method of claim36, wherein the placing the semiconductor die includes securing thesemiconductor die to a die paddle located within the plurality of leads.39. The method of claim 36, wherein the severing is effected by making alinear cut between the spaced locations on each lead extending from acommon peripheral edge.
 40. The method of claim 39, further comprisingnotching upper surfaces of the leads between the spaced locations beforethe placing the semiconductor die within the plurality of leads, andwherein the linear cut is extended substantially only to a depthsufficient to intersect bottoms of the notches so that some dielectricmaterial remains between the spaced locations.
 41. A lead frame strip,comprising: a plurality of longitudinally arranged lead frames, eachlead frame including an outer frame portion bearing a plurality ofinwardly extending, cantilevered leads, and each lead of the pluralityhaving thereon at least two longitudinally spaced locations separated bya severance region comprising a notch extending laterally across thelead.
 42. The lead frame strip of claim 41, wherein each outer frameportion further bears a die paddle substantially centered therein. 43.The lead frame strip of claim 41, wherein the plurality of inwardlyextending, cantilevered leads are located on a plurality of sides ofeach outer frame portion.
 44. The lead frame strip of claim 41, whereinthe plurality of inwardly extending, cantilevered leads are located onfour sides of each outer frame portion.